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specifications of any and all sanyo semiconductor co.,ltd. products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer ' s products or equipment. to verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer ' s products or equipment. any and all sanyo semiconductor co.,ltd. products described or contained herein are, with regard to "standard application", intended for the use as general electronics equipment. the products mentioned herein shall not be intended for use for any "special application" (medical equipment whose purpose is to sustain life, aerospace instrument, nuclear control device, burning appliances, transportation machine, traffic signal system, safety equipment etc.) that shall require extremely high level of reliability and can directly threaten human lives in case of failure or malfunction of the product or may cause harm to human bodies, nor shall they grant any guarantee thereof. if you should intend to use our products for new introduction or other application different from current conditions on the usage of automotive device, communication device, office equipment, industrial equipment etc. , please consult with us about usage conditi on (temperature, operation time etc.) prior to the intended use. if there is no consultation or inquiry before the intended use, our customer shall be solely responsible for the use. 30712hkpc 20120124-s00002 no.a2009-1/24 LC72121MA overview the LC72121MA are high input sensitiv ity (20mvrms at 130mhz) pll freque ncy synthesizers for 3v systems. these ics are serial data (ccb) compatible with the lc72131k/kma, and feature the improved input sensitivity and lower spurious radiation (provided by a redesigned ground system) required in high-performance am/fm tuners. features ? high-speed programmable divider ? fmin: 10 to 160mhz pu lse swallower technique (with built-in divide-by-2 prescaler) ? amin: 2 to 40mhz pu lse swallower technique 0.5 to 10mhz direct division technique ? if counter ? ifin: 0.4 to 15mhz for am and fm if counting ? reference frequency ? one of 12 reference frequencies can be select ed (using a 4.5 or 7.2mhz crystal element) 1, 3, 5, 9, 10, 3.125, 6.25, 12.5, 15, 25, 50, and 100khz ? phase comparator ? supports dead zone control. ? built-in unlocked state detection circuit ? built-in deadlock clear circuit ? an mos transistor for an active low-pass filter is built in. ? i/o ports ? output-only ports: 4 pins ? i/o ports: 2 pins ? supports the output of a clock time base signal. ? serial data i/o ? support ccb format communicatio n with the system controller. ? operating ranges ? supply voltage: 2.7 to 3.6v ? operating temperat ure: -40 to +85c ? package ? mfp24sj ? ccb is a registered trademark of sanyo semiconductor co., ltd. ? ccb is sanyo semiconductor's original bus format. all bus addresses are managed by sanyo semiconductor for this format. cmos ic pll frequency synthesizers for electronic tuning ordering number : ena2009
LC72121MA no.a2009-2/24 specifications absolute maximum ratings at ta = 25 c, v ssd = v ssa = v ssx = 0v parameter symbol conditions ratings unit maximum supply voltage v dd max v dd -0.3 to +7.0 v v in 1 max ce, cl, di, ain -0.3 to +7.0 v v in 2 max xin, fmin, amin, ifin -0.3 to v dd +0.3 v maximum input voltage v in 3 max io1 , io2 -0.3 to +15 v v o 1 max do -0.3 to +7.0 v v o 2 max xout, pd -0.3 to v dd +0.3 v maximum output voltage v o 3 max bo1 to bo4 , io1 , io2 , aout -0.3 to +15 v i o 1 max do, aout 0 to 6.0 ma maximum output current i o 2 max bo1 to bo4 , io1 , io2 0 to 10 ma allowable power dissipation pd max (ta 85 c) 200 mw operating temperature topr -40 to +85 c storage temperature tstg -55 to +125 c note 1: power pins v dd and v ss : insert a capacitor with a capacitance of 2,000pf or higher between these pins when using the ic. allowable operating ranges at ta = -40 to +85 c, v ssd = v ssa = v ssx = 0v ratings parameter symbol pin conditions min typ max unit supply voltage v dd v dd 2.7 3.6 v v ih 1 ce, cl, di 0.7v dd 6.5 v input high-level voltage v ih 2 io1 , io2 0.7v dd 13 v input low-level voltage v il ce, cl, di, io1 , io2 0 0.3v dd v v o 1 do 0 6.5 v output voltage v o 2 bo1 to bo4 , io1 , io2 , aout 0 13 v f in 1 xin v in 1 1.0 8.0 mhz f in 2 fmin v in 2 10 160 mhz f in 3 amin v in 3(sns=1) 2.0 40 mhz f in 4 amin v in 4(sns=0) 0.5 10 mhz input frequency f in 5 ifin v in 5 0.4 15 mhz guaranteed crystal oscillator frequency x ? tal xin, xout note 2 4.0 8.0 mhz v in 1 xin f in 1 200 800 mvrms v in 2-1 fmin f=10 to 130mhz 20 800 mvrms v in 2-2 fmin f=130 to 160mhz 40 800 mvrms v in 3 amin f in 3(sns=1) 40 800 mvrms v in 4 amin f in 4(sns=0) 40 800 mvrms v in 5 ifin f in 5(ifs=1) 40 800 mvrms input amplitude v in 6 ifin f in 5(ifs=0) 70 800 mvrms data setup time t su di, cl note 3 0.75 s data hold time t hd di, cl note 3 0.75 s clock low level time t cl cl note 3 0.75 s clock high level time t ch cl note 3 0.75 s ce wait time t el ce, cl note 3 0.75 s ce setup time t es ce, cl note 3 0.75 s ce hold time t eh ce, cl note 3 0.75 s data latch change time t lc note 3 0.75 s t dc do, cl data output time t dh do, ce differs depending on the value of the pull-up resistor. note 3 0.35 s
LC72121MA no.a2009-3/24 note 2: recommended crystal oscillator ci values: ci 120 (for a 4.5mhz crystal) ci 70 (for a 7.2mhz crystal) the characteristics of the oscillation circuit depends on the printed circuit board, circuit constants, and other factors. therefore we recommend cons ulting with the anufacturer of the crystal for evaluation and reliability. note 3: refer to "serial data timing". electrical characteristics in the allowable operating ranges ratings parameter symbol pin conditions min typ max unit rf1 xin 1.0 m rf2 fmin 500 k rf3 amin 500 k internal feedback resistance rf4 ifin 250 k rpd1 fmin 100 200 400 k internal pull-down resistance rpd2 amin 100 200 400 k hysteresis v his ce, cl, di 0.1v dd v output high-level voltage v oh pd i o =-1ma v dd -1.0 v v ol 1 pd i o =1ma 1.0 v i o =1ma 0.2 v v ol 2 bo1 to bo4 , io1 , io2 i o =8ma 1.6 v i o =1ma 0.2 v v ol 3 do i o =5ma 1.0 v output low-level voltage v ol 4 aout i o =1ma, ain=1.3v 0.5 v i ih 1 ce, cl, di v i =6.5v 5.0 a i ih 2 io1 , io2 v i =13v 5.0 a i ih 3 xin v i =v dd 1.3 8 a i ih 4 fmin, amin v i =v dd 2.5 15 a i ih 5 ifin v i =v dd 5.0 30 a input high-level current i ih 6 ain v i =6.5v 200 na i il 1 ce, cl, di v i =0v 5.0 a i il 2 io1 , io2 v i =0v 5.0 a i il 3 xin v i =0v 1.3 8 a i il 4 fmin, amin v i =0v 2.5 15 a i il 5 ifin v i =0v 5.0 30 a input low-level current i il 6 ain v i =0v 200 na i off 1 bo1 to bo4 , aout, io1 , io2 v o =13v 5.0 a output off leakage current i off 2 do v o =6.5v 5.0 a high-level 3-state off leakage current i offh pd v o =v dd 0.01 200 na low-level 3-state off leakage current i offl pd v o =0v 0.01 200 na input capacitance c in fmin 6 pf i dd 1 v dd x?tal=7.2mhz f in 2=130mhz v in 2=20mvrms 2.5 6 ma i dd 2 v dd pll block stopped (pll inhibit mode) crystal oscillator operating (crystal frequency: 7.2 mhz) 0.3 ma supply current i dd 3 v dd pll block stopped. crystal oscillator stopped. 10 a
LC72121MA no.a2009-4/24 package dimensions unit : mm (typ) 3419 pin assignment sanyo : mfp24sj(300mil) 1 24 13.0 0.45 8.0 6.0 0.15 1.0 0.4 (1.0) 1.9 max 0.1 (1.5) 2 top view 13 14 15 16 17 18 19 20 21 22 24 1 2 3 4 5 6 7 8 9 10 11 12 xout ifin v ssd amin fmin v dd pd ain aout v ssa ce v ssx xin do cl nc di bo3 bo2 bo1 io1 bo4 23 nc LC72121MA io2
LC72121MA no.a2009-5/24 block diagram pd ifin amin ce di cl do v ssd v dd fmin xout xin universal counter unlock detector phase detector charge pump reference divider data shift register latch 12bits programmable divider swallow counter 1/16,1/17 4bits power on reset ccb i/f 1/2 ain v ssa aout bo1 v ssx bo2 bo3 bo4 io1 io2
LC72121MA no.a2009-6/24 pin descriptions pin name pin no. type function equivalent circuit xin xout 1 24 x?tal osc ? crystal oscillator element co nnections (4.5 or 7.2 mhz) fmin 17 local oscillator signal input ? fmin is selected when dvs in the serial data is set to 1. ? input frequency: 10 to 160mhz ? the signal is passed through an internal divide-by-two prescaler and then input to the swallow counter. ? the divisor can be set to a value in the range 272 to 65535. since the internal divide-by-two prescaler is used, the actual divisor will be twice the set value. amin 16 local oscillator signal input ? amin is selected when dvs in th e serial data is set to 0. ? when sns in the serial data is set to 1: ? input frequency: 2 to 40mhz ? the signal is input to the swallow counter directly. ? the divisor can be set to a value in the range 272 to 65535. the set value becomes the actual divisor. ? when sns in the serial data is set to 0: ? input frequency: 0.5 to 10mhz ? the signal is input to a 12-bit programmable divider directly. ? the divisor can be set to a val ue in the range 4 to 4095. the set value becomes the actual divisor. ce 3 chip enable ? this pin must be set high to enable serial data input (di) or serial data output (do). di 4 input data ? input for serial data trans ferred from the controller cl 5 clock ? clock used for data synchronization for serial data input (di) and serial data output (do). do 6 output data ? output for serial data transmitted to the controller. the content of the data transmitted is determined by doc0 through doc2. v dd 18 power supply ? LC72121MA power supply (v dd 2.7 to 3.6v) ? the power on reset circuit operates when power is first applied. - v ssx 2 ground ? ground for the crystal oscillator circuit - v ssd 15 ground ? ground for the LC72121MA digital systems other than those that use v ssa or v ssx . - bo1 bo2 bo3 bo4 7 8 9 10 output port ? output-only ports ? the output state is determined by bo1 through bo4 in the serial data. when the data value is 0: the output state will be the open circuit state. when the data value is 1: the output state will be a low level. ? a time base signal (8hz) is output from bo1 when tbc in the serial data is set to 1. io1 io2 11 14 i/o port ? shared function i/o ports ? the pin function is determined by ioc1 and ioc2 in the serial data. when the data value 0: input port when the data value 1: output port ? when specified to function as an input port: the input pin state is reported to the controller through the do pin. when the input state is low: the data will be 0: when the input state is high: the data will be 1: ? when specified to function as an output port: the output state is determined by io1 and io2 in the serial data. when the data value is 0: the output state will be the open circuit state. when the data value is 1: the output state will be a low level. ? these pins are set to input mode after a power on reset. continued on next page. s s s
LC72121MA no.a2009-7/24 continued from preceding page. pin name pin no. type function equivalent circuit pd 19 charge pump output ? pll charge pump output a high level is output when the fr equency of the local oscillator signal divided by n is higher than the reference frequency, and a low level is output when that frequency is lower. this pin goes to the highimpedance state when the frequencies match. ain aout 20 21 low-pass filter amplifier transistor ? connections for the mos transistor used for the pll active low-pass filter. v ssa 22 ground ? ground for the low-pass filter mos transistor ifin 13 if counter ? the input frequency range is 0.4 to 15mhz ? the signal is passed directly to the if counter. ? the result is output, msb first, through the do pin. ? four measurement periods are s upported: 4, 8, 32, and 64ms. nc 12 23 nc pin ? no connection -
LC72121MA no.a2009-8/24 procedures for input and output of serial data this product uses the ccb (computer control bus), which is sanyo?s audio product serial bus format, for data input and output. this product adopts an 8-bit address ccb format. address i/o mode b0 b1 b2 b3 a0 a1 a2 a3 function [1] in1(82) 0 0 0 1 0 1 0 0 ? control data input (serial data input) mode ? 24 bits of data are input. ? see the ?di control data (serial data input)? section for details on the content of the input data. [2] in2(92) 1 0 0 1 0 1 0 0 ? control data input (serial data input) mode ? 24 bits of data are input. ? see the ?di control data (serial data input)? section for details on the content of the input data. [3] out(a2) 0 1 0 1 0 1 0 0 ? data output (serial data output) mode ? the number of bits output is equal to the number of clock cycles. ? see the ?do output data (serial dat a output)? section for details on the content of the output data. (2) (1) first data in1/2 first data out first data out a3 a2 a1 a0 b3 b2 b1 b0 di i/o mode determined ce cl (2) (1) cl:normally high (2) cl:normally low (1) do
LC72121MA no.a2009-9/24 structure of the di control data (serial data input) [1] in1 mode [2] in2 mode r2 r1 r0 (3) if-ctr xs cte dvs sns p15 p14 p13 p12 p11 p10 (1) p-ctr (2) r-ctr p9 p8 p7 p6 p5 p4 p3 p2 p1 p0 r3 address 0 0 1 0 1 0 0 di 0 first data in1 test1 test0 ifs (12) test (11) ifs (10) pd-c (5) o-port (13) don?t care (6) do-c (9) time dlc tbc gt1 gt0 dz1 dz0 ul1 ul0 doc2 doc1 (7) unlock (4) io-c (8) dz-c (3) if-ctr doc0 dnc bo4 bo3 bo2 bo1 io2 io1 ioc2 ioc1 test2 address 0 0 1 0 1 0 0 di 1 first data in2
LC72121MA no.a2009-10/24 control data no. control block/data function related data (1) programmable divider data p0 to p15 dvs, sns ? specifies the divisor for the programmable divider. this is a binary value in which p15 is the msb. the lsb changes depending on dvs and sns. (* : don?t care) dvs sns lsb set divisior (n) actual divisior 1 0 0 * 1 0 p0 p0 p4 272 to 65535 272 to 65535 4 to 4095 twice the set value the set value the set value * lsb : when p4 is the lsb, p0 to p3 are ignored. ? these pins select the signal input to the pr ogrammable divider (fmin or amin) and switch the input frequency range. (* : don?t care) dvs sns input pin frequency range accepted by the input pin 1 0 0 * 1 0 fmin amin amin 10 to 160mhz 2 to 40mhz 0.5 to 10mhz * see the ?structure of the programmable divider? section for details. (2) reference divider data r0 to r3 xs ? reference frequency selection r3 r2 r1 r0 reference frequency 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 100 khz 50 25 25 12.5 6.25 3.125 3.125 1 1 1 1 0 0 0 0 0 0 1 1 0 1 0 1 10 9 5 1 1 1 1 1 0 0 0 1 3 15 1 1 1 0 * pll inhibit+x?tal osc stop 1 1 1 1 * pll inhibit * pll inhibit mode in this mode, the programmable divider and th e if counter block are stopped, the fmin, amin, and ifin pins are pulled down to ground, and the charge pump output goes to the high- impedance state. ? crystal oscillator element selection data xs = 0: 4.5mhz xs = 1: 7.2mhz note that 7.2 mhz is selected after a power on reset. (3) if counter control data cte gt0, gt1 ? if counter measurement start command data cte = 1 : starts the counter cte = 0 : resets the counter ? if counter measurement time. gt1 gt0 measurement time wait time 0 0 1 1 0 1 0 1 4 ms 8 32 64 3 to 4 ms 3 to 4 7 to 8 7 to 8 * see the ?structure of the if counter? section for details. ifs (4) i/o port setup data ioc1,ioc2 ? specifies input or output for the shared function i/o pins ( io1 and io2 ). data = 0: input port data = 1: output port (5) output port data bo1 to bo4 io1,io2 ? determines the output state of the bo1 through bo4 , io1 , and io2 output ports. data = 0: open data = 1: low level ? the data is reset to 0, setting the pins to the open state, after a power on reset. ioc1 ioc2 continued on next page.
LC72121MA no.a2009-11/24 continued from preceding page. no. control block/data function related data (6) do pin control data doc0 doc1 doc2 ? determines the do pin output. doc2 doc1 doc0 do pin state 0 0 0 0 0 0 1 1 0 1 0 1 open low when the pll is unlocked end-uc *1 open 1 1 1 1 0 0 1 1 0 1 0 1 open the io1 pin state *2 the io2 pin state *2 open the open state is selected after a power on reset. *1. end-uc: if counter measurement end check (1)when end-uc is selected and an if count is started (by switching cte from 0 to 1), the do pin automatically goes to the open state. (2)when the if counter measurement period complete s, the do pin goes to the low level, allowing applications to test for the completion of the count period. (3)the do pin is set to the open state by perform ing a serial data input or output operation (when the ce pin is set high). *2. the do pin will go to the open state if the corresponding io pin is set up to be an output port. note) during the data input period (the period that ce is high in in1 or in2 mode), the do pin goes to the open state regardless of the do pin control data (doc0 to doc2). during the data output period (the period that ce is high in out mode) the do pin state reflects the internal do serial data in synchronization with the cl clock, regardless of the do pin control data (doc0 to doc2). ul0, ul1 cte ioc1 ioc2 (7) unlocked state detection data ul0, ul1 ? selects the width of the phase error ( e) detected for pll lock state discrimination. the state is taken to be unlocked if a phase error in excess of the detection width occurs. ul1 ul0 e detection width detection output 0 0 1 1 0 1 0 1 stop 0 0.55 s 1.11 s open e is output directly e is extended by 1 to 2ms * when the pll is unlocked, the do pin goes low and ul in the serial data output is set to 0. doc0 doc1 doc2 (8) phase comparator control data dz0, dz1 ? controls the phase comparator dead zone dz1 dz0 dead zone mode 0 0 1 1 0 1 0 1 dza dzb dzc dzd dead zone width: dza < dzb < dzc < dzd (9) clock time base tbc ? setting the tbc bit to 1 causes an 8-hz clock time base signal with a 40% duty to be output from the bo1 pin. (the bo1 data will be ignored.) bo1 (10) charge pump control data dlc ? forcibly controls the charge pump output. dlc charge pump output 0 1 normal operation forced low * if the circuit deadlocks due to the vco cont rol voltage (vtune) being 0 and the vco being stopped, applications can get out of the deadlocked state by setting the charge pump output to low and setting vtune to v cc . (deadlock clear circuit) (11) if counter control data ifs ? this data is normally set to 1. setting this data to 0 sets the circuit to reduced input sensitivity mode, in which the sensitivity is reduced by about 10 to 30mv rms. * see the ?if counter operation? section for details. (12) test data test0 to 2 ? test data test0 test1 all these bits must be set to 0. test2 all these bits are set to 0 after a power on reset. (13) dnc ? this bit must be set to 0. (1) count start ce:high (2) count end do pin
LC72121MA no.a2009-12/24 structure of the do output data (serial data output) [3] out mode control data functions no. control block/data function related data (1) i/o port data i2, i1 ? data latched from the i/o port io1 or io2 pin states. ? these bits reflect the pin states regardless of the i/o port mode (input or output). the data is latched at the point the circui t enters data output mode (out mode). i1 the io1 pin state high : 1 i2 the io2 pin state low : 0 ioc1 ioc2 (2) pll unlocked state data ul ? indicates the state of the unl ocked state detection circuit. ul 0: when the pll is unlocked. ul 1: when the pll is locked or in the detection disabled mode. ul0 ul1 (3) if counter binary counter c19 to c0 ? indicates the value of the if counter (20-bit binary counter). c19 msb of the binary counter c0 lsb of the binary counter cte gt0 gt1 c1 c2 c3 (2) unlock (1) in-port c4 c5 c6 c7 c8 c9 c10 c11 c12 c13 (3) if-ctr c14 c15 c16 c17 c18 c19 ul * i1 i2 c0 address fist data out 0 0 1 0 1 0 1 do *: data with the value 0 di 0
LC72121MA no.a2009-13/24 1.serial data input (in1/in2) t su , t hd , t es , t eh , 0.75 s t lc < 0.75 s (1) cl: normally high (2) cl: normally low 2.serial data output (out) t su , t hd , t el , t es , t eh , 0.75 s t dc , t dh < 0.35 s (1) cl: normally high (2) cl: normally low note: the data conversion times (t dc and t dh ) depend on the value of the pull-up resistor and the printed circuit board capacitance since the do pin is an n-channel open-drain circuit. internal data t lc t eh t es t el t hd t su r3 r2 r1 p3 p2 p1 p0 a3 a2 a1 a0 b3 b2 b1 b0 r0 di ce cl internal data t lc t eh t es t el t hd t su r3 r2 r1 p3 p2 p1 p0 a3 a2 a1 a0 b3 b2 b1 b0 r0 di ce cl do di ce cl t dc t dc t dh t eh t es t el t hd t su ul i1 i2 a3 a2 a1 a0 b3 b2 b1 b0 c0 c1 ce c3 do t dc t dc t dh t eh t es t el t hd t su i1 i2 ul a3 a2 a1 a0 b3 b2 b1 b0 c0 c1 c2 c3 di ce cl
LC72121MA no.a2009-14/24 serial data timing when cl is stopped at the low level when cl is stopped at the high level t ch t eh t es t hd t su old new t lc t dh t dc t el t cl v il v il v ih v ih v ih v ih v ih v ih v il v il v il do internal data latch cl di ce t cl t eh t es t hd t su old new t lc t dh t dc t dc t el t ch v il v il v il v ih v ih v ih v ih v ih v ih v il v il v il do internal data latch cl di ce
LC72121MA no.a2009-15/24 structure of the programmable divider dvs sns input pin set divisor ac tual divisor input frequency range (a) (b) (c) 1 0 0 * 1 0 fmin amin amin 272 to 65535 272 to 65535 4 to 4095 twice the set value the set value the set value 10 to 160mhz 2 to 40mhz 0.5 to 10mhz *: don?t care sample programmable divider divisor calculations (1) for fm with a step size of 50khz (dvs = 1, sns = *: fmin selected) fm rf = 90.0mhz (if +10.7mhz) fm vco = 100.7mhz pll fref = 25khz (r0 to r1 = 1, r2 to r3 = 0) 100.7mhz (fm vco) 25khz (fref) 2 (for the fmin 1/2 prescaler) = 2014 07de (hexadecimal) (2) for sw with a step size of 5khz (dvs = 0, sns = 1: amin high-speed operation selected) sw rf = 21.75 mhz (if +450khz) sw vco = 22.20mhz pll fref = 5khz (r0 = r2 = 0, r1 = r3 = 1) 22.2mhz (sw vco) 5khz (fref) = 4440 1158 (hexadecimal) (3) for mw with a step size of 9khz (dvs = 0, sns = 0: amin low-speed operation selected) mw rf = 1008khz (if +450khz) wm vco = 1458khz pll fref =9khz (r0 = r3 = 1, r1 = r2 = 0) 1458 (mw vco) 9khz (fref) = 162 0a2 (hexadecimal) (a) (c) (b) sns dvs 4bits 12bits swallow counter programmable divider fvco = fref n fref fvco/n pd
LC72121MA no.a2009-16/24 structure of the if counter the LC72121MA if counter is a 20-bit binary counter, and takes the if signal from the ifin pin as its input. the result of the count can be read out serially, msb first, from the do pin. measurement time gt1 gt0 measurement time (gt) wait time (t wu ) 0 0 1 1 0 1 0 1 4 ms 8 32 64 3 to 4 ms 3 to 4 7 to 8 7 to 8 the if frequency (fc) is measured by determining how many pulses were input to the if counter in the stipulated measurement time, gt. fc = c gt (c=fc gt) c: counted value (the number of pulses) if counter frequency measurement examples (1) when the measurement time (gt) is 32ms and the counted value (c) is 53980 (hexadecimal) or 342,400 (decimal). if frequency (fc) = 342400 32ms = 10.7mhz (2) when the measurement time (gt) is 8ms and the coun ted value (c) is e10 (hexad ecimal) or 3600 (decimal). if frequency (fc) = 3600 8ms = 450khz 4/8/32/64 ms 8 to 11 4 to 7 0 to 3 16 to 19 12 to 15 (fc) (c) (gt) gt0 m s b l s b if counter (20-bits binary counter) c = fc gt cte do pin gt1 ifin i2 i1 0 8 9 3 5 ul c19 c18 c17 c16 c15 c14 c13 c12 c11 c10 c9 c8 c7 c6 c5 c4 c3 c2 c1 c0 01 0 1 0 011100110000 0 0 0 i2 i1 0 1 e 0 0 ul c19 c18 c17 c16 c15 c14 c13 c12 c11 c10 c9 c8 c7 c6 c5 c4 c3 c2 c1 c0 00 0 0 0 000111000010 0 0 0
LC72121MA no.a2009-17/24 if counter operation applications must first, before starting an if count operation reset the if counter by setting cte in the serial data to 0. the if counter operation is started setting cte in the serial da ta from 0 to 1. although the serial data is latched by dropping the ce pin from high to low, the if signal input to the ifin pin must be provided within the wait time from the point ce goes low. next, the readout of the if counter after measurement is complete must be performed while cte is still 1, since the counter will be reset if cte is set to 0. note: if if counting is used, applications must determine whet her or not the if ic sd (station detect) signal is present in the microcontroller software, and perform the if count only if that signal is asse rted. this is because auto- search techniques that use if counting only are subject to incorrect stopping at points where there is no station due to if buffer leakage. note that the LC72121MA input sensitivity can be controlled with the ifs bit in the serial data. reduced sensitivity mode (ifs = 0) must be selected when this ic is used in conjunction with an if ic that does not provide an sd output and auto-search is implemented using only if counting. ifin minimum sensitivity standard input frequency : f [mhz] ifs data 0.4 f < 0.5 0.5 f < 8 8 f 15 1 (normal mode) 40mvrms (0.1 to 3m vrms) 40mvrms 40mvrms(1 to 15mvrms) 0 (degraded sensitivity mode) 70mvrms(5 to 10mvrms) 70mvrms 70mvrms(30 to 40mvrms) note: values in parentheses are actual performance values that are provided for reference purposes. data with cte 1 count start count end (end-uc) gt wait time measurement time ifin frequency measurement time ce
LC72121MA no.a2009-18/24 unlocked state detection 1. unlocked state detection timing unlocked state detection is performed during the reference frequency (fref) period (interval). this means that a period at least as long as the period of the reference fre quency is required to recognize the locked/unlocked state. however, applications must wait at leas t twice the period of the reference fre quency immediately after changing the divisor (n) before checking the locked/unlocked state. figure 1 unlocked state detection timing for example, if fref is 1khz (a period of 1ms) applications must wait at least 2 ms after the divisor n is changed before performing a locked/unlocked check. figure 2 circuit structure new divisor n old divisor n new data old data * after changing the value of the divisor, the error signal will be output following the second period of the fref signal. do not change the divisor n in the first period. n- counter error phase comparator data latch n unlocked state detection circuit r preset vco/n fref
LC72121MA no.a2009-19/24 2. combining with software figure 3 combining with software 3. outputting the unlocked st ate data in the serial data at the point of data output 1 in figure 3, the unlocked state data will indicate the unlocked state, since the vco frequency is not stable (locked) yet. in cases such as this , the application should wait at least one whole period and then check again whether or not the frequency has stabili zed with the data output 2 operation in the figure. applications can implement even more reliable recognition of the locked state by performing several more checks of the state and requiring that the lock ed state be detected sequentially. < flowchart for lock detection > 4. directly outputting the un locked state to the do pin since the unlocked state (high level when locked, low when unlocked) is output from the do pin, applications can check for the locked state by waiting at least two referen ce frequency periods after changing the divisor n. however, in this case also, even more reliable recognition of the lo cked state can be achieved by performing several checks of the state and requiring that the lock ed state be detected sequentially. vco frequency error divisor n unlocked detection pin output unlocked state output in the serial data ce data output (2) data input data output (1) new data old data locked locked unlocked valid output data is acquired by using an interval of at least one reference frequency period. *: even more reliable recognition of the locked state can be achieved by perfor ming several checks of the state and requiring that the locked state be detected sequentially. wait at least 2 reference frequency periods. divisor n changed (data input) locked state check * no yes data output (2) data output (1)
LC72121MA no.a2009-20/24 clock time base usage notes when using the clock time base output function, the output pin ( bo1 ) pull-up resistor must have a value of over 100k . the use of a schmitt input in the microcontroller that accepts this signal is recommended to reduce chattering. this is to prevent degradation of the vco c/n characteristics when combining with a loop filter that uses the internal transistor provided to form a low-pass filter. a lthough the ground for the clock time base output pin (v ssd ) and the ground for the transistor (v ssa ) are isolated internally on the chip, appli cations must take care to avoid ground loops and minimize current fluctuations in the time base pin to prevent degradation of the lo w-pass filter characteristics. other items (1) notes on the phase comparator dead zone dz1 dz0 dead zone mode charge pump dead zone 0 0 dza on/on --0s 0 1 dzb on/on -0s 1 0 dzc off/off +0s 1 1 dzd off/off ++0s when the charge pump is used with one of the on/on modes, correction pulses are generated from the charge pump even if the pll is locked. as a result, it is easy for th e loop to become unstable, and special care is required in application design. the following problems can occur if an on/on mode is used. (1) sidebands may be created by reference frequency leakage. (2) sidebands may be created by low-frequency leakage due to the correction pulse envelope. although the loop is more stable when a dead zone is pr esent (i.e. when an off/off m ode is used), a dead zone makes it more difficult to achieve excellent c/n characteristic s. on the other hand, while it is easy to achieve good c/n characteristics when there is no dead zone, achieving good loop stability is difficult. accordingly, the dza and dzb settings, in which there is no dead zone, can be effec tive in situations where a signal-to-noise ratio of 90 to 100db or higher is required in fm reception, or where it is desirable to increase the pilot margin in am stereo reception. however, if such a high signal-to-noise ratio is not required for fm reception, if an adequate pilot margin can be acquired in am stereo reception, or if am stereo is not required, then either dzc or dzd, in which there is a dead zone, should be chosen. v cc v ssa vco vt v dd pd ain aout v ssd v ssd bo1 rt 100k schmitt input microcontroller s LC72121MA loop filter time base output
LC72121MA no.a2009-21/24 dead zone as shown in figure 1, the phase comparator compares a re ference frequency (fr) with fp. as shown in figure 2, the phase comparator's characteristics consist of an output vo ltage (v) that is proportional to the phase difference . however, due to internal circuit delay and other factors, an actual circuit has a region (the dead zone, b) where the circuit cannot actually compare th e phases. to implement a receiver with a high s/n ratio, it is desirable that this region be as small as possible. however, it is often desirable to have the dead zone be slightly wider in popularly-priced models. this is because in certain cases, such as when th ere is a strong rf input, popul arly-priced models can suffer from mixer to vco rf leakage that modulates the vco. when the dead zone is small, the circuit outputs signals to correct this modulation and this output further modulates the vco. this further modulation may then generate beats and the rf signal. figure 1 figure 2 (2) notes on the fmin, amin, and ifin pins coupling capacitors should be placed as close to their pin as possible. a capacitance of about 100pf is desirable for these capacitors. in particular , if the ifin pin coupling capacitor is not he ld under 1000pf, the time to reach the bias level may become excessive and incorrect counts may result due to the relationship with the wait time. (3) notes on if counting use the sd signal in conjunction with if counting when counting the if frequency, the microcontroller must determine the presence or absence of the if ic sd (station detect) signal and turn on the if counter buffer output and execute the if count only if there is an sd signal. autosearch techniques that only use the if counter are subj ect to incorrect stopping at points where there is no station due to if buffer leakage. (4) do pin usage the do pin can be used for if counter count completion checking and as an unlock detection output in addition to its use in data output mode. it is also possible to have the do pin reflect the state of an input pin to input that state to the microcontroller. (5) power supply pins capacitors must be inserted between the power supply v dd and v ss pins for noise exclusion. these capacitors must be placed as close as possible to the v dd and v ss pins. (6) vco setup applications must be designed so that the vco (local oscillator) does not stop, even if the control voltage (vtune) goes to 0v. if it is possible for the oscillator to stop, the application must use the contro l data (dlc) to temporarily force vtune to v cc to prevent deadlock from occurring. (dead lock clear circuit) reference divider vco lpf programmable divider phase detector mix rf leakage fr fp
LC72121MA no.a2009-22/24 (7) front end connection example since this product is designed with the relatively high resistance of 200k for the pulldown (on) resistors built in to the fmin and amin pins, a common am/fm local oscillator bu ffer can be used as shown in the following circuit. (8) pd pin note that the charge pump output voltage is reduced when this ic, which is a 3-v system, is used to replace the lc72131k/kma, which is a 5-v system. this means that sin ce the loop gain is reduced, the loop filter constants, the lock time (sd wait time), and other related parameters must be reevaluated in the end product design. pin states after a power on reset fm osc fmin osc buffer out on resistance: 200k amin fe pll on resistance: 200k am osc input port v ssa aout ain pd xout v dd LC72121MA fmin amin io2 v ssd bo4 bo3 bo2 bo1 do cl di ce xin v ssx open input port open open open open ifin io1 nc nc
LC72121MA no.a2009-23/24 sample applications circuit 1 xin 24 xout 23 nc 2 22 v ssa 3 ce 21 aout 4 di 20 ain 5 cl 19 pd 6 do 12 nc ce di cl do 18 v dd 7 bo1 17 fmin 8 bo2 16 amin 9 bo3 15 v ssd 10 bo4 14 io2 11 io1 13 ifin v ssx s s s LC72121MA -com unlock sd end-uc ifcount st-indic amvco fmvco am/fm-if tuner-system sd if-request fm/am mono/st st-indicate v cc
LC72121MA no.a2009-24/24 ps sanyo semiconductor co.,ltd. assumes no responsib ility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all sanyo semiconductor co.,ltd. products described or contained herein. sanyo semiconductor co.,ltd. strives to supply high-quality high-reliab ility pr oducts, however, any and all semiconductor products fail or malfunction with some probab ility. it is possible that these pr obab ilistic failures or malfunction could give rise to accidents or events that could endanger human lives, trouble that could give rise to smoke or fire, or accidents that could cause dam age to other property. when designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. upon using the technical information or products described herein, neither warranty nor license shall be granted with regard to intellectual property rights or any other rights of sanyo semiconductor co.,ltd. or any third party. sanyo semiconductor co.,ltd. shall not be liable for any claim or suits with regard to a third party's intellctual property rights which has resulted from the use of the technical information and products mentioned above. any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. when designing equip ment, refer to the "delivery specification" for the sanyo semiconductor co.,ltd. product that you intend to use. in the event that any or all sanyo semiconductor co.,ltd. products described or contained herein are controlled under any of applicable local export control laws and regulations, such products may require the export license from the authorities concerned in accordance with the above law. no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written consent of sanyo semiconductor co.,ltd. this catalog provides information as of march, 2012. specifications and information herein are subject to change without notice.

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